module ctr_bench;

    reg [4:0]   inst;
    wire [1:0]  regdst;
    wire [2:0]  ext;
    wire [3:0]  aluop;
    wire        regwr;
    wire        memrd;
    wire        memwr;
    wire        memtoreg;
    wire        alusrc2;
    wire [2:0]  branch;
    wire        j;
    wire        jr; 
    wire        createdump;
    wire        lbi;
    
    wire [79:0]   str[31:0];
    assign  str[0] = "halt";
    assign  str[1] = "nop";
    assign  str[2] = "siic";
    assign  str[3] = "nop/rti";
    assign  str[4] = "j";
    assign  str[5] = "jr";
    assign  str[6] = "jal";
    assign  str[7] = "jalr";
    assign  str[8] = "addi";
    assign  str[9] = "subi";
    assign  str[10] = "xori";
    assign  str[11] = "andni";
    assign  str[12] = "beqz";
    assign  str[13] = "bnez";
    assign  str[14] = "bltz";
    assign  str[15] = "bgez";
    assign  str[16] = "st";
    assign  str[17] = "ld";
    assign  str[18] = "slbi";
    assign  str[19] = "stu";
    assign  str[20] = "roli";
    assign  str[21] = "slli";
    assign  str[22] = "rori";
    assign  str[23] = "srli";
    assign  str[24] = "lbi";
    assign  str[25] = "btr";
    assign  str[26] = "rol/..";
    assign  str[27] = "add/..";
    assign  str[28] = "seq";
    assign  str[29] = "slt";
    assign  str[30] = "sle";
    assign  str[31] = "sco";

    ctr U0 (
            .inst(inst),
            .regdst(regdst),
            .ext(ext),
            .aluop(aluop),
            .memrd(memrd),
            .memwr(memwr),
            .memtoreg(memtoreg),
            .alusrc2(alusrc2),
            .branch(branch),
            .j(j),
            .jr(jr),
            .createdump(createdump),
            .lbi(lbi),
            .regwr(regwr)
           );

    integer k;
    initial
    begin
        for (k=0; k<=31; k=k+1)
            #5  inst = k;
        #10 $finish;
    end

    //string s[31:0] = {32{"hello"}};
    always @(inst)
    begin   
        #1;
        $display("%b %s regdst=%b ext=%b aluop=%b reg.wr=%b mem.rd/wr=%b memtoreg=%b alusrc=%b branch=%b j=%b jr=%b lbi=%b createdump=%b",
                inst,str[inst],regdst,ext,aluop,regwr,{memrd,memwr},memtoreg,alusrc2,branch,j,jr,lbi,createdump);
    end
endmodule
